1. Field of the Invention
The present invention relates to data communications. More particularly, the present invention relates to data communications using current signals.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a conventional current mode transmitter.
Referring to FIG. 1, the current mode transmitter determines a logic state of an output signal Iout according to the voltage of the output signal Iout, which varies between a high power supply voltage Vcc and a low power supply voltage GND. To embody the current mode transmitter, a circuit for generating two bias voltages Pbias and Nbias is additionally required to supply the voltages to the current mode transmitter. Thus, the structure of the current mode transmitter is complicated, and power dissipation is increased, since current is continuously supplied from the high power supply voltage Vcc, is sunk to the low power supply voltage GND or sinks irrespective of a state of the output signal Iout.
FIG. 2 is a circuit diagram of another conventional current mode transmitter.
Referring to FIG. 2, the current mode transmitter has an open drain structure in which the drain of a metal oxide silicon (MOS) transistor is open, and an output signal Iout depends on the amount of sink current supplied from an output port. The transmitter shown in FIG. 2 has been proposed to reduce power dissipation as compared with the transmitter shown in FIG. 1.
When current flowing through a MOS transistor M3 is cut off by an inverted input signal Vinb, the current flowing through a MOS transistor M2 is cut off. Thus, only a current of Iref−ΔI flowing through a MOS transistor M1 is supplied from the output port. On the other hand, when current flows through the MOS transistor M3 by the inverted input signal Vinb, a current of 2ΔI flows through the MOS transistor M2. Thus, a current of Iref+ΔI is supplied from the output port. For example, to determine a logic state of an output signal Iout according to the amount of current supplied from the output port, when current supplied from the output port is Iref−ΔI, Iout can be defined as a logic high, and when the current from the output port is Iref+ΔI, Iout can be defined as a logic low.
In the transmitter shown in FIG. 2, since only one bias voltage Bias is used, a circuit for generating the bias voltage Bias is simpler than in the transmitter of FIG. 1 using two bias voltages Pbias and Nbias. Also, as only one power supply voltage GND is used in the transmitter of FIG. 2, power dissipation can be reduced.
In FIG. 2, the MOS transistor M2 operates in a saturation region or a cut-off region according to the voltage of the inverted input signal Vinb. While the operating region of the MOS transistor M2 switches between the saturation region and the cut-off region, channel charges are generated or disappear to vary a voltage drop in a parasitic capacitor Cgs that exists between the gate and the source of the MOS transistor M2. The variation of the voltage drop in the parasitic capacitor Cgs changes the amount of the current flowing through the MOS transistor M2 and finally causes transmission errors. The parasitic capacitor Cgs is generated when a MOS transistor is produced, and the capacitance of the parasitic capacitor Cgs depends on the width and the length of the gate of the MOS transistor.
FIG. 3 is a waveform diagram illustrating the output current of the conventional transmitter shown in FIG. 2.
In the conventional transmitter, two output current states, Iref+ΔI and Iref−ΔI, are generated according to the voltage of the inverted input signal Vinb. The operating region of each MOS transistor included in the current mode transmitter alternately switches between the saturation region and the cut-off region, thereby exhibiting the two output current states Iref+ΔI and Iref−ΔI.
Referring to FIG. 3, while each MOS transistor is alternately switching between the two operation regions, the rising and falling edges of the output current Iout collapse due to the variation in channel charges of the MOS transistor. This collapse phenomenon shows that the waveform of the output current is not the same as that of an input voltage.
Referring to FIGS. 2 and 3, when the inverted input signal Vinb switches from a high state to a low state, a rise in the voltage of the node X lags, thus resulting in a cut-off delay of the MOS transistor M2. The cut-off delay results in a delay in switching of the output current. As a result, a duty ratio of a current signal to be transmitted is deteriorated.